1. Field of the Invention
The present invention relates to a semiconductor memory device having a test mode circuit.
2. Description of the Related Art
Recently, semiconductor memory devices have been designed with increasingly larger memory capacities. With this increase in memory capacity, the time needed for testing whether the semiconductor memory cells function properly also tends to increase. Unfortunately, this increase in time, in turn, results in higher testing costs. It is consequently desirable to shorten the time needed for testing.
FIG. 1 exemplifies the data output section of a conventional semiconductor memory device equipped with a test mode circuit. Read data bar D1 to bar Dn of n bits from selected memory cells are input to n latch circuits L1 to Ln bit by bit. The latch circuits L1-Ln latch the read data bar D1-bar Dn and output those data as latched data DL1 to DLn to a data compressor 1 and a decoder 2. The latched data DL1-DLn compressed by data compressor 1 includes, for example, eight bits to one bit. The results, as compressed data, are output as signal .phi.DC. In detail, the data compressor 1 outputs an H-level output signal .phi.DC to a selector 3 when 8-bit latched data DL1-DLn have the same value, and outputs an L-level output signal .phi.DC to the selector 3 when otherwise. The decoder 2 receives a column address signal AD based on which, the decoder 2 selects one of the latched data DL1-DLn and outputs it as an output signal .phi.DD to the selector 3.
The selector 3 also receives a test mode signal .phi.T, which goes high during any testing operation, i.e., during any test mode. When the H-level test mode signal .phi.T is input to the selector 3, the selector 3 outputs the output signal .phi.DC of the data compressor 1 as an output signal .phi.DATA to an output circuit 4. In a normal mode, which differs from that of the test mode, a L-level test mode signal .phi.T is input to the selector 3. Based on this L-level test mode signal .phi.T, the selector 3 outputs the output signal .phi.DD of the decoder 2 as the output signal .phi.DATA to the output circuit 4. The output circuit 4 receives an output control signal .phi.RSD. When this signal .phi.RSD goes high, the output circuit 4 is activated to output the output signal .phi.DATA of the selector 3 as an output signal Dout.
FIG. 2 graphically illustrates the operation of the above described data output section. In normal mode, the test mode signal .phi.T is at a L level. Reading operations start when control signal bar RAS falls. The output control signal .phi.RSD goes high after a predetermined time from the falling of the control signal bar RAS, while the output circuit 4 is activated in response to the H-level output control signal .phi.RSD. Subsequently, read data bar D1 to bar Dn, read from the selected memory cells, are latched by the respective latch circuits L1 to Ln, which then output the output signals DL1 to DLn. The decoder 2 outputs one of the output signals DL1-DLn from the latch circuits L1-Ln as the output signal .phi.DD, based on the column address signal AD. The selector 3 sends out the output signal .phi.DD of the decoder 2 as the output signal .phi.DATA to the output circuit 4, which then outputs this signal .phi.DATA as the output signal Dout.
In test mode, the test mode signal .phi.T first goes high, and then the reading operation starts at the timing of the falling of the control signal bar RAS. In test mode, since the same data has already been written in the individual memory cells, the output control signal .phi.RSD goes high after a predetermined time from the falling of the control signal bar RAS. This renders the output circuit 4 active. Subsequently, read data bar D1 to bar Dn, read from the selected memory cells, are latched by the respective latch circuits L1 to Ln, which then output the output signals DL1 to DLn. The data compressor 1 compresses the latched data DL1-DLn, for example, eight bits to one bit, and outputs the resultant data. More specifically, the data compressor 1 either, outputs an H-level output signal .phi.DC when the 8-bit latched data DL1-DLn coincide with each another, or outputs an L-level output signal .phi.DC when those data do not match with one another. The selector 3 outputs signal .phi.DC of the data compressor 1 as signal .phi.DATA to the output circuit 4. Circuit 4, in turn, outputs this signal .phi.DATA as the output signal Dout.
Such a data output section as described above cannot perform an operational test on the individual memory cells to measure the access time required for the simultaneous reading of data during a test mode. During a test of the individual memory cells, all the memory cells have the same data previously provided to them. Consequently, the cell information read from each memory cell should be the same. When the individual memory cells properly function, the output signals DL1 to DLn from the latch circuits L1 to Ln always have the same value, and the output signal .phi.DC, which is output from the data compressor 1 based on the output signals DL1-DLn, should always go high. Consequently, if the individual memory cells are functioning properly, the output signal Dout of the output circuit 4 goes high based on the old data latched by the individual latch circuits L1-Ln. Then, the output signal Dout is kept at the H level based on new data that is read out at the falling of the control signal bar RAS. Since the level of the output signal Dout is kept high, it is impossible to measure the access time required for a reading operation from when the control signal bar RAS falls till that time when the output signal Dout is output.
Due to this restriction, semiconductor memory devices containing the above-described data output section design, must measure cell access time in a procedure separate from that for testing the function of the memory cells. Measuring cell access time is accomplished by reading data bit by bit without using the test mode. If there is a possibility that old cell data coincides with new cell data, access time can not be measured accurately. At the time of measuring the access time, therefore, data different from the data to be read out should be held previously in the latch circuits L1 to Ln. Due to this restriction, the above-described test mode for allowing the data compressor 1 to compress and check the output signals DL1 to DLn of the latch circuits L1-Ln cannot be used. Therefore, it is necessary to measure the access times for many memory cells individually. This increases the time needed for testing the memory function and increases the testing costs.